MCU Embedded software

Embedded Software Design for Processors Based on ARM, MCS51, and RISC-V Architectures

Embedded software design involves developing efficient and reliable software tailored for specific hardware architectures to meet the functional requirements of a device. Below is an overview of the characteristics and design methodologies for processors based on ARM, MCS51, and RISC-V architectures.

1. ARM Architecture

Characteristics:

• High Performance and Low Power: Widely used in IoT, smartphones, and embedded systems.
• Multiple Instruction Sets: Supports ARM, Thumb, and Thumb-2 instruction sets.
• Multi-core Support: Common in real-time task scheduling systems.
• Rich Peripherals: Includes built-in DMA, GPIO, timers, UART, SPI, etc.
• Toolchain Support: Compatible with various tools (Keil, IAR, GCC, etc.).

Design Methodology:

1. Startup File Design:
   • ARM systems use a startup file to initialize stack pointers, allocate interrupt vector tables, and set up system peripherals.
   • The CMSIS library (Cortex Microcontroller Software Interface Standard) simplifies hardware access.
2. RTOS Integration:
   • ARM processors are often paired with RTOS (e.g., FreeRTOS, RT-Thread) to handle real-time requirements.
   • Configure the SysTick timer as the RTOS system tick.
3. Driver Development:
   • Develop peripheral drivers using HAL (Hardware Abstraction Layer) or direct register access.
   • Optimize low-power modes (e.g., Sleep, Deep Sleep).
4. Low-Power Design:
   • Use ARM Cortex-M series instructions like WFI/WFE to enter low-power states.
   • Configure power management registers (e.g., PWR) for sleep and wake-up control.

2. MCS51 Architecture

Characteristics:

• 8-bit Microcontroller: A classic architecture suitable for simple, low-cost embedded systems.
• Limited Resources: Typically features small RAM and ROM (e.g., 256 bytes of RAM, 8 KB of ROM).
• Single-Cycle Instruction Set: Optimized for basic control logic tasks.
• Programming Languages: Supports C and assembly.

The above image shows commonly used, higher-performance, and low-cost MCS51 MCU STC 15Wxxx

Design Methodology:

1. Startup File Design:
   • Initialize the stack pointer (SP), configure interrupt priorities, and initialize peripherals.
   • Startup code is usually written directly in the main C file without a complex startup file.
2. Interrupt-Driven Design:
   • Leverage MCS51’s simple interrupt priority mechanism for moderately time-sensitive tasks.
   • Configure interrupt registers (e.g., IE, TCON) for peripherals like Timers and UART.
3. Memory Optimization:
   • Use lightweight C compilers (e.g., Keil C51) and memory models (data, idata, xdata) to optimize resource usage.
   • Avoid dynamic memory allocation and prefer static variables.
4. Low-Power Design:
   • Use the chip’s power management features to enter idle or power-down modes.

3. RISC-V Architecture

Characteristics:

• Open-Source Architecture: Highly extensible and suitable for customization.
• Modular Instruction Set: Supports a base integer set (RV32I/64I) and extensions (e.g., RV32M, RV32F).
• High Portability: Applicable to devices ranging from microcontrollers to high-performance processors.
• Toolchain Support: Compatible with GNU toolchains (GCC, GDB) and LLVM.

The above image is of Nanjing Qinheng Microelectronics Co., Ltd. RISC-V: CH32V.

Design Methodology:

1. Startup File Design:
   • Startup code is typically written in assembly to configure the stack pointer and initialize memory.
   • Load .text, .data, and .bss sections, and set up interrupt vector tables.
2. Interrupt and Exception Handling:
   • Configure the interrupt controller (e.g., PLIC: Platform-Level Interrupt Controller).
   • Use M-mode (Machine Mode) for critical exceptions, with S-mode/U-mode for task segregation.
3. RTOS Support:
   • FreeRTOS supports RISC-V; implementation requires handling timer interrupts and context switching.
   • Configure RISC-V CSR (Control and Status Registers) for system state management.
4. Performance Optimization:
   • Utilize hardware multiplication/division extensions (M extension) and floating-point extensions (F extension).
   • Optimize instruction execution efficiency through cache management and pipeline tuning.

General Design Principles

1. Memory Optimization:
   • For resource-constrained devices, avoid dynamic memory allocation.
   • Use DMA to offload CPU tasks.
2. Real-Time Assurance:
   • Properly configure interrupt priorities and minimize task switching delays.
   • For high-priority real-time tasks, consider bare-metal programming.
3. Low-Power Design:
   • Disable unused peripheral clocks.
   • Use low-power modes and configure wake-up sources appropriately.
4. Debugging and Testing:
   • Use debugging tools (e.g., JTAG/SWD) for code testing and validation.
   • Perform unit testing to ensure reliability of software modules.